AXRHSTS=Val_0x0, AXWHSTS=Val_0x0, TPS0=Val_0x0, RPS0=Val_0x0
Debug Status 0 Register
| AXWHSTS | AXI Master Write Channel When high, this bit indicates that the write channel of the AXI master is active, and it is transferring data. 0 (Val_0x0): AXI master write channel status not detected 1 (Val_0x1): AXI master write channel status detected |
| AXRHSTS | AXI Master Read Channel Status When high, this bit indicates that the read channel of the AXI master is active, and it is transferring the data. 0 (Val_0x0): AXI master read channel status not detected 1 (Val_0x1): AXI master read channel status detected |
| RPS0 | DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0. The MSB of this field always returns 0. This field does not generate an interrupt. 0 (Val_0x0): Stopped (reset or stop receive command issued) 1 (Val_0x1): Running (fetching Rx transfer descriptor) 3 (Val_0x3): Running (waiting for Rx packet) 4 (Val_0x4): Suspended (Rx descriptor unavailable) 5 (Val_0x5): Running (closing the Rx descriptor) 6 (Val_0x6): Timestamp write state 7 (Val_0x7): Running (transferring the received packet data from the Rx buffer to the system memory) |
| TPS0 | DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0. The MSB of this field always returns 0. This field does not generate an interrupt. 0 (Val_0x0): Stopped (reset or stop transmit command issued) 1 (Val_0x1): Running (fetching Tx transfer descriptor) 2 (Val_0x2): Running (waiting for status) 3 (Val_0x3): Running (reading data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) 4 (Val_0x4): Timestamp write state 6 (Val_0x6): Suspended (Tx descriptor unavailable or Tx buffer underflow) 7 (Val_0x7): Running (closing Tx descriptor) |